This invention relates to a method of manufacturing a semiconductor integrated circuit device, and more particularly, to a method of manufacturing a so-called "BI-MOS" integrated circuit device in which both a MOS element and a bipolar element are formed on one and the same chip.
In general, bipolar elements are high in drive capacity per chip area, and can process analog data with high accuracy. However, bipolar elements also have a relatively low degree of integration, and low input impedances. On the other hand, among the features of MOS elements are high input impedances and a large degree of integration. Accordingly, it is advantageous to form a MOS element on a chip which essentially includes a bipolar element, such that the above-described drawbacks of the bipolar elements are neutralized. One typical example in the prior art of such a device is a so-called "MOS top operational amplifier" in which a MOS element is formed in the input stage of the bipolar element. In such BI-MOS integrated circuit devices, an npn transistor is employed as the bipolar element, and a p-channel MOS transistor is employed as the MOS element. A conventional method of manufacturing such a BI-MOS integrated circuit will now be described in further detail, with reference to FIG. 1.
As shown in FIG. 1(A), after layers 2 of n-type high impurity concentration are formed on a p-type silicon substrate 1, an epitaxial layer 3 of n-type low impurity concentration is grown onto the layers 2 and the substrate (1). Then, as shown in FIG. 1(B), oxidation is selectively carried out with an oxidation resisting film 4 such as a nitride operating as a mask, so that thick oxide films 5 are formed which electrically isolate the element forming regions 3a and 3b in the epitaxial layer 3 from each other.
In FIG. 1(C), the nitride film 4 is then removed, and an oxide film 6 is formed as a protective film for implanting ions. A photo-resist film 7 is formed, and boron ions are implanted into the semiconductor surface through the oxide film 6 with the photo-resist film 7 serving as a mask. The photo-resist film 7 is removed, and the boron ions are subjected to driving diffusion by heat treatment, such that a p-type base layer 8, a source layer 9, a drain layer 10 and a diffusion resistor (not shown) are formed in the epitaxial layer 3. Then, as shown in FIG. 1(D), a collector contact n+ layer 11 and an emitter n+ layer 12, which are both of n-type high impurity concentration are formed by ion implantation or gas diffusion. Next, as in FIG. 1(E), an oxide film 13 such as a phospho-silicate-glass film is deposited. The parts of the oxide film 13 and 6 where a gate should be formed are then removed, and a gate oxide film 14 is formed therein. Finally, as shown in FIG. 1(F), after windows are opened in the oxide film 13 and 6 to provide the electrodes, a base electrode 15, an emitter electrode 16, a collector electrode 17, a source electrode 18, a gate electrode 19, and a drain electrode 20 are formed along with the various other necessary connecting wires (not shown).
In general, when manufacturing a BI-MOS integrated circuit device, it is essential to control the characteristic parameters of each element with high accuracy. Among the characteristic parameters which must be thus controlled are:
(1) the junction breakdown voltage of each element,
(2) the current amplification factor (h.sub.FE) of the npn transistor, and/or the current amplification factor (h.sub.FE) of the pnp transistor,
(3) the threshold voltage (Vth) of the p-channel MOS transistor, and
(4) the resistance (R) of the diffusion resistor.
In the process above-described as shown in FIGS. 1(A)-1(F), after the n+ emitter diffusion has been accomplished, a high temperature heat treatment is carried out to form the gate oxide film. By virtue of this subsequent heat treatment, the n+ layer as diffused is distributed again; that is, the n+ layer diffuses further into the p+ layer. Accordingly, it is very difficult to control the h.sub.FE of the npn transistor in the bipolar circuit with high accuracy. This is the most serious problem involved in manufacturing a BI-MOS integrated circuit.
In order to overcome this difficulty, the h.sub.FE of the npn transistor has been controlled highly accurately in the prior art by the following methods:
(a) Merely accounting for the variation of h.sub.FE due to the subsequent heat treatment by allowing the n+ layer to only diffuse so far;
(b) In the n+ emitter diffusion, only allowing the n+ deposition to be carried out; that is, the n+ layer is merely deposited, without being allowed to diffuse into the p+ layer. After all the heat treatment required for forming the MOS gate oxide film is carried out, the heat treatment for the n+ layer is then carried out in an inert atmosphere; and
(c) forming the gate oxide film of the MOS element at low temperature, after the n+ emitter diffusion.
These methods, while achieving high control of h.sub.FE, present drawbacks of their own. For instance, in method (a), since the heat treatment carried out thereafter typically greatly fluctuates, it is difficult to estimate the amount of variations of h.sub.FE with high reproducibility. In method (b), during the subsequent heat treatment with inert gas, Vth of the MOS element becomes unstable. Finally, in method (c), it is difficult to accurately control the levels of the silicon substrate and the gate oxide film of the MOS element, again producing instabilities in Vth of the MOS element.